The present invention relates to semiconductor devices operative in a relatively low frequency range such as 1 to 3 GHz for the mobile communication, and more particularly to a circuit arrangement suitable for implementation in the form of a microwave monolithic integrated circuit device including a high performance power amplifier for a sending unit of a mobile terminal which has an FET having a large gate width.
In order to reduce a mobile communication terminal in size, in addition to reduction of a battery and a signal processing LSI included in the terminal, it will be necessary to reduce function devices used in a radio unit (sending/receiving unit), such as a power amplifier, a low noise amplifier, a frequency converter, and a bandpass filter.
Each of these function devices unavoidably involves matching circuits at the I/O stages for higher performance of the radio unit of the mobile communication terminal. In order to reduce the radio unit in size, the circuit components of the matching circuit efforts have bee made such that a leadless resistor, a leadless capacitor and a leadless inductor are made smaller, highly packaged and formed on a multilayered wiring substrate. For further size reduction, it will be a technical trend that the matching circuits used are implemented in a microwave monolithic integrated circuit in which some parts of the matching circuit such as active elements (FETs) are formed on a semiconductor substrate.
A matching circuit to be formed in a microwave monolithic IC device includes thin film capacitors, spiral inductors, and distributed lines. Among them, the spiral inductors and the distributed lines will occupy a large area. In developing microwave monolithic IC devices, efforts have been concentrated to how to use properly these main components from the viewpoint of the high performance, operation frequency and occupation area and size reduction.
The power amplifier needs an FET having a large gate width for obtaining a large output power. As the gate width is made larger, the output impedance of the FET is made lower accordingly. Hence, even a slight resistance appearing in the signal propagating direction may lower a power gain.
Thus, for a high operation performance of the spiral inductor in the matching circuit, it is desirable to reduce a series parasitic resistance appearing in the signal propagating direction. For this purpose, it is necessary to widen the conductor for forming the spiral inductor. To obtain an intended inductance from such a conductor, outer dimensions of the inductor will be larger.
In realizing an intended impedance with a spiral inductor or a distributed line, as the operation frequency is made higher, outer dimensions of the spiral inductor and the line length of the distributed line may be made smaller. However, the line length of the distributed line has a greater dependency on the operation frequency than that of the outer dimension of the spiral inductor. In order to obtain the same impedance at a low frequency such as 1 to 3 GHz, the line length of the distributed line will have to be made abruptly longer.
On the other hand, the spiral inductor unavoidably provides a parasitic capacity such as an inter-line capacity and an earth capacity in light of its structure. Hence, the use of the spiral inductor is limited to operation frequencies lower than its resonant frequency. Thus, it is not used at high frequencies such 5 to 10 GHz.
As described above, in arranging the circuit, the spiral inductors and the distributed lines are required to be properly used by considering the operation frequency range and the allowable occupation area of the function device of the radio unit.
As reported in the Technical Report SAT 84-1 of the Institute of Electronics, Information and Communication Engineers of Japan (IEIC) published on May 29, 1984, pp. 1-7, the power amplifier used for a super high frequency band of 10 to 30 GHz does not employ the spiral inductor because the spiral inductor has a resonance frequency lower than 10 GHz. Hence, the power amplifier is realized in a microwave monolithic IC device formed on a single chip in which matching circuits for the input and the output stages are both made of distributed lines.
However, for a relatively low operation frequency such as 1 to 3 GHz, if the power amplifier employs only distributed lines, the distributed line would have a relatively long line length, which results in a large chip area. In this case, since this frequency band is lower than the resonant frequency of a spiral inductance of a lumped constant, the spiral inductor may be employed in the power amplifier. As described in page 2-615 of 1994 Spring Meeting C-110 of IEIC, therefore, the power amplifier employs a circuit arrangement in which the spiral inductors and the distributed lines are mingled. The matching circuit for an input stage and the inter-stage matching circuit use spiral inductors. Between a drain electrode of the final-stage FET and an output signal terminal provided in the output matching circuit for the final stage, a distributed line is formed so that a series parasitic resistance towards the signal propagation, which will undesirably lower the electric power gain, may be relatively easily reduced by widening the distributed line. With the conventional design method, the overall length of the distributed line for supplying a drain voltage for the final stage FET is made to be a quarter of a wavelength .lambda. of the effective wavelength of the operation frequency, because an impedance seen at the drain electrode towards the power supply is infinity for thereby preventing leakage of an output signal to the power supply. When the operation frequency is 1.9 GHz, a line length of .lambda./4 is as long as about 11 mm. Such a long distributed line is not allowed to be formed on one and the same substrate. Further, the length is too large for the distributed line even to be attached to the outside of the substrate. In place of the distributed line, therefore, the used circuitry is arranged so that a spiral inductor of a lumped constant is attached to the outside of the substrate. Nevertheless, as described in this publication, the chip size is as large as 2.7 mm.times.2.7 mm. The circuitry described in page 2-612 of 1994 Spring Meeting C-110 of IEIC is arranged so that the output matching circuit at the final stage is made of a distributed line formed on another substrate having a high dielectric constant rather than the semiconductor substrate having the FETs formed thereon.